In a camera system, data of a series of images acquired by an imaging device is processed by an image processing device, and the series of processed images are sequentially displayed by a display device. In order to process the images on the basis of the operation timing of the image processing device, input image data for one frame is completely stored in a memory of the image processing device, and then the image processing device performs image processing on the stored image data, and holds the stored data in the memory until the image processing device completes the image processing on the stored image data.
During the image processing, the next image data is input to the image processing device from the imaging device. In order to inhibit image data that is currently processed from being broken, a plurality of memory spaces (hereinafter referred to as banks) that are configured to store images are prepared. When the image processing device completely stores input image data for one frame in a single bank, the image processing device stores image data for the next frame in another bank. In this case, the bank is switched to the other bank in order to store the image data by switching management addresses (that are each a starting address of a memory space for one frame, for example) of the banks configured to store image data.
In each of many camera systems, the timing of starting an operation of an imaging device is not synchronous with the timing of starting an operation of an image processing device. In addition, in each of the camera systems, time intervals between times when the imaging device performs a process are different from time intervals between times when the image processing device performs image processing in many cases. In general, in each of the camera systems, an oscillator for the imaging device is different from and independent of an oscillator for the image processing device. In each of the camera systems, even when oscillation frequencies of both oscillators are equal to each other according to design specifications of the oscillators, the actual operation timing of the imaging device does not completely match the actual operation timing of the image processing device owing to an error. In order to synchronize the imaging device with the image processing device, a mechanism for performing communication control, a phase-locked loop, or the like is provided. In this case, however, there is a problem with the cost. Thus, there is a demand for a system to be designed so that there is no practical problem even when an imaging device and an image processing device are not synchronized with each other.
For example, Japanese Laid-open Patent Publication No. 08-214131 discloses a method in which two buffer memories are alternately switched and data is read and transferred simultaneously. In addition, for example, Japanese Laid-open Patent Publication No. 10-322643 discloses that two or more physical banks are ensured in a frame memory and image data is written in the physical banks and read from the physical banks in order to display the image data.